1. Field of the Invention
This invention relates to semiconductor structures and more particularly to a semiconductor transistor structure having a unique emitter structure and an improved gain.
2. Description of the Prior Art
Semiconductor transistor structures are well known in the art. Traditionally, to form an NPN structure, a highly doped N+ subcollector region is diffused into a major surface of a semiconductor substrate. An epitaxial layer is then deposited over the substrate. The subcollector partially out-diffuses into the epitaxial layer during the deposition of this layer. A base region with a P-type impurity is then diffused into the epitaxial layer in contact with the subcollector region. An N-type impurity, such as arsenic or phosphorus, for example, is then diffused into the base region forming an emitter region of the transistor. The emitter region is wholly contained beneath the surface and within the base region of the epitaxial layer.
The preferred method, for reasons of economics and control, for diffusing an impurity to form the emitter region is by ion implanation. The use of ion implanation to form an emitter region in the base region of the epitaxial layer, however, has led to numerous problems.
During ion implantation, the monocrystalline nature of the epitaxial layer is disrupted as a consequence of the radiation damage. After completion of the ion bombardment, the crystalline structure is restored by subjecting the material to an annealing heat treatment. While the annealing heat treatment is sufficient to restore most of the disrupted structure, some residual damage of the structure remains. These crystalline defects can cause impaired performance of the transistor device. Moreover, the annealing heat treatment causes the implanted doping ions to migrate further into the base region. The drive-in of the implanted doping ions results in providing an emitter depth that is greater than desired. The juxtaposition of the emitter sidewall with the base adjacent the emitter sidewal results in providing parasitic capacitance that is higher than desired.
A further problem is that subsequent metallization of the emitter takes place on the surface of the epitaxial layer. The usual method is to deposit platinum onto the silicon surface at the face of the emitter. Subsequent treatment results in providing platinum silicide at the surface. The silicon for forming the platinum silicide is "stolen" from the silicon of the epitaxial layer and lateral growth of the platinum silicide inherently occurs. Such lateral growth can result in shorting of the emitter to the base at the surface. Because of the extremely small spaces utilized in forming semiconductor transistor structures, such possibility of emitter shorting is a real and continuing problem.
It would be desirable to provide a transistor with a reduced emitter to base sidewall contact so as to reduce parasitic capacitance engendered between the emitter and base. It would also be desirable to provide a transistor structure with a shallower emitter wherein the emitter is at least partially isolated from the base region. A transistor with a smaller emitter can switch from conduction to nonconduction and vice versa faster. It would also be desirable to provide an emitter structure wherein metallization takes place at a location remote from possible bridging contact so as to reduce penetration difficulties.